Compute derating factor
Since R2020a
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Libraries:
Motor Control Blockset / Controls / Controllers
Motor Control Blockset HDL Support / Controls / Controllers
Description
The Derating Function block generates the derating factor (y
) according to the feedback (ffeedback
) and maximum limit (fmax
) values of the input reference signal.
The derating factor:
Remains equal to one when
ffeedback
lies between positive and negative values of the Derating threshold. The derating factor varies linearly outside this range according toffeedback
.Remains equal to zero when the reference signal lies beyond (positive or negative)
fmax
.
Therefore, you can use the generated derating factor to derate a control signal after the reference signal crosses the specified Derating threshold.
This figure shows the block output when you use a sinusoidal wave as ffeedback
.
Equations
The Derating threshold parameter, indicates the percentage of peak amplitude for the reference signal. The Derating threshold is 0.5 in the block output shown, which results in a threshold value of 2 (for the peak amplitude value of 4 for the sinusoidal reference signal).
This equation describes how the block computes the derating factor (y
).
Ports
Input
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fmax — Maximum reference signal limit
scalar
Maximum limit of the reference signal value beyond which the derating factor becomes zero.
Data Types: single
| double
| fixed point
ffeedback — Reference feedback signal
scalar
Reference signal that the block uses to generate the derating factor, which you can then use to derate a control signal.
Data Types: single
| double
| fixed point
Output
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y — Derating factor
scalar
Derating factor that the block generates based on the feedback and maximum limit values of the reference signal when the signal exceeds the value of the Derating threshold parameter.
Data Types: single
| double
| fixed point
Parameters
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Derating threshold — Threshold beyond which derating must occur
0.9
(default) | scalar in the range [0,1)
The reference signal value beyond which the block generates the derating factor.
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
HDL Architecture
This block has one default HDL architecture.
HDL Block Properties
ConstrainedOutputPipeline | Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is |
InputPipeline | Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is |
OutputPipeline | Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is |
Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.
Version History
Introduced in R2020a